1. Field of the Invention
The present invention generally relates to semiconductor devices, and in particular to the fabrication of a semiconductor device including process of lapping a semiconductor layer to a desired layer thickness with high precision, including the excellent control of the flatness and uniformity of the semiconductor layer. The present invention is particularly useful when applied to fabrication of semiconductor devices having the so-called SOI (silicon-on-insulator) substrate. However, the present invention is by no means limited to such particular semiconductor devices.
2. Description of Related Art
The SOI substrates are known as an effective structure for providing a nearly ideal device isolation in integrated circuits. In SOI substrates, a semiconductor layer is provided on an insulator layer that may be a mechanically rigid insulator plate or provided on an insulator layer that is provided on another mechanically rigid semiconductor substrate. Semiconductor devices are formed on the semiconductor layer on the insulator layer. By segmenting the semiconductor layer in correspondence to the semiconductor devices, various preferable features such as increased breakdown voltage, elimination of latch-up in complementary metal-oxide-silicon (CMOS) devices, reduction of the so-called soft errors and the like, can be achieved. Particularly, when the layer thickness of the semiconductor layer on which the semiconductor devices are formed is reduced, the parasitic capacitance associated with the semiconductor layer is decreased, and thereby one can obtain an increased operational speed of the semiconductor device.
There are several different processes to produce the SOI substrate. For example, there is a so-called SIMOX process, wherein oxygen atoms are implanted into a silicon substrate at a controlled depth from the surface such that there is formed an insulator layer of oxide underlying a silicon layer that, in turn, is used as an active semiconductor layer in which active devices are formed. Further, there is known a process including steps of depositing a polysilicon layer on an insulator substrate such as silicon oxide and subsequently crystallizing the polysilicon layer by annealing. However, any of these processes has the problem in that the quality of the semiconductor layer obtained on the insulator layer is not satisfactory.
There is a third process known for producing the SOI substrate, wherein a single crystal semiconductor layer, having an oxide layer on the surface, is bonded with another single crystal semiconductor layer that also has the surface formed with an oxide layer. The bonding is made by intimately contacting the side of both semiconductor layers on which the oxide layer is formed with each other such that there is formed an intervening oxide layer between the pair of semiconductor layers. Further, a heat treatment is applied such that there is formed a polymerization of sianol bonds at the contacting oxide layers. With this process, the semiconductor layer for use as a part of the active device has the quality that is equivalent to that of the bulk semiconductor layer and an excellent device characteristic is guaranteed.
In the SOI substrate produced by the last mentioned process, the semiconductor layer is lapped subsequently to a desired layer thickness. For example, the layer thickness of the semiconductor layer is reduced from about 600-700 .mu.m to about several microns by lapping. Recently, there is a demand to reduce the layer thickness further to 0.1-5 .mu.m such that the operational speed of the semiconductor device is further improved. As already noted, the operational speed of the semiconductor device is improved by reducing the layer thickness of the active semiconductor layer as a result of the decreased parasitic capacitance.
When the lapping process is applied to the SOI substrate to reduce the thickness of the semiconductor layer to such an extent, however, there arises a case in which the lapping may proceed inhomogeneously or somewhat obliquely. When this occurs particularly in a wafer having a large diameter, a part of the semiconductor layer may be totally removed or the layer thickness of the semiconductor layer may become inhomogeneous.
In order to avoid the problem, it has been practiced to provide a so-called stopper or lapping stopper of a material that resists the mechanical lapping on a suitable location of the surface of the semiconductor layer such that the lapping proceeds uniformly over the entire surface of the semiconductor layer. For example, the stopper may be provided in correspondence to the dicing line of the semiconductor wafer.
FIGS. 1A and 1B show the conventional process of lapping the SOI substrate using the lapping stopper.
Referring to FIG. 1A, the SOI substrate comprises a single crystal silicon layer 31 acting as the foundation of the SOI structure. On the silicon layer 32, a silicon oxide layer 32 is formed and another single crystal silicon layer 33 is provided on the silicon oxide layer 32. As already explained, the substrate 31 and the silicon layer 33 are bonded with the intervening silicon oxide layer 32.
On the silicon oxide layer 33, there is provided a groove 34 in correspondence to the dicing line such that the silicon oxide layer 32 is exposed at the groove 36. Further, there is provided a lapping stopper 35 of a material like silicon oxide or other hard material that resists lapping, on the silicon oxide layer 32 in correspondence to the groove 34. Because of the possible deviation from the ideal alignment, the lapping stopper 35 cannot be provided to fill the groove 34 completely but is made to be smaller in width as compared with the width of the groove 34. Thereby, it should be noted that there is formed a gap 36 in the groove 34 generally at both sides of the lapping stopper 35.
The structure of FIG. 1A may be produced by bonding the silicon layer 31 and the silicon layer 33 as already described and subsequently grinding the silicon layer 33 to a thickness of about several microns. The initial thickness of the silicon layer 33 may be several hundred microns. Next, the groove 34 is formed by applying the reactive ion etching (RIE) process such that the semiconductor layer 33 is selectively removed in correspondence to the groove 34. The etching is continued until the silicon oxide layer 32 is exposed. Next, a silicon layer not illustrated is deposited on the entire surface of the SOI substrate by a CVD process to a predetermined thickness and subsequently patterned, for example by the RIE process. The patterning is conducted such that the lapping stopper 35 is left in the groove 34 with the gaps 36 formed at both sides of the lapping stopper 35. As already explained, the gap 36 is provided to avoid the possible misalignments at the time of patterning, and thereby it is guaranteed that no silicon oxide is remained on the surface of the silicon oxide layer 33.
Next, the structure of FIG. 1A is subjected to the mechanical lapping. Thereby, the thickness of the semiconductor layer 33 is reduced until the top surface of the layer 33 becomes flush with the top surface of the lapping stopper 35 as shown in FIG. 1B. Once the state of FIG. 1B is achieved, further decrease in the thickness of the layer 33 by etching is resisted by the lapping stopper 35 that is characterized by an increased hardness or decreased lapping rate as compared with silicon.
In this conventional approach, there exists an obvious problem in that a gently declining surface 37 tends to develop in the semiconductor layer 33 at both sides of the lapping stopper 35. With the existence of the declining surface 37, the semiconductor layer 33 gradually reduces the thickness toward the lapping stopper 35. This is because the existence of the gap 36 facilitates the lapping at the edge part of the groove 34 and thereby the edge part of the groove 34 is preferentially removed. This region having the declining surface 37 has a lateral extension x that may reach as much as several hundred microns. Obviously, such reduction in the thickness of the semiconductor layer 33 near the groove 34 causes a change in the depth of the diffusion regions formed in the layer 33, and thereby there is a substantial risk that the characteristic of the semiconductor device is changed in the region near the groove 34. As the lateral extension x of the region that has the declining surface 37 is in the order of several hundred microns, the effect of such a decrease in the thickness of the semiconductor layer 33 on the device characteristic is by no means negligible. Conventionally, the extension x cannot be decreased below about 100 .mu.m even when one uses a hard cloth for the lapping.
FIGS. 2A-2C show another conventional example of the lapping stopper that is disclosed in the Japanese Laid-open Patent Application No. 1-136328. As the process for forming the structure including the silicon substrate 31 and the silicon layer 33 with the intervening silicon oxide layer 32 and the groove 34 is identical with the step of forming the structure of FIG. 1A, the description for this part will be omitted.
According to this approach, a silicon oxide layer 35a is deposited by the CVD process with a uniform thickness on the semiconductor layer 33 including the groove 34. In correspondence to the groove 34, there is formed a depression 41 on the surface of the silicon oxide layer 35a. This depression 41 is subsequently filled by a photoresist 42, and using the photoresist 42 as a mask, the silicon oxide layer 35a is subjected to the RIE process. Thereby, the RIE process is controlled such that the etching is stopped when the silicon oxide layer 35a filling the gap 36 has a top surface that is exactly flush with the surface of the silicon oxide layer embedded underneath the photoresist 42. In other words, a silicon oxide layer that has a flat upper surface is obtained in the groove 34 as the lapping stopper 35 as shown in FIG. 2B.
Next, the photoresist 42 is removed and the structure thus obtained is subjected to a lapping process until the top surface of the semiconductor layer 33 becomes flush with the top surface of the lapping stopper 35 as shown in FIG. 2C. In this process, it is possible to obtain a completely flat upper surface of the semiconductor layer 33. In other words, the undesirable gap 36 of the previous example is eliminated from this structure and the formation of the declining surface 37 near the groove 34 is eliminated.
It should be noted that this approach relies upon the exact control of the RIE process to obtain the flat upper major surface of the lapping stopper 35. In other words, the RIE process has to be controlled in a extremely exact manner such that there is no insufficient etching or excessive etching of the silicon oxide layer 35a. When the etching is insufficient, a structure shown in FIG. 3A is obtained wherein there is formed a depression 35b surrounded by side walls 35c of increased height or thickness. Such a side wall 35c of silicon oxide is mechanically fragile and may come off upon further lapping. When this occurs, such silicon oxide debris inevitably causes scars on the surface of the thin silicon layer 33. Such scars would be detrimental to the device characteristic of the semiconductor device formed on the silicon layer 33. On the other hand, when the etching is performed excessively, a structure shown in FIG. 3A is obtained wherein there is formed the gap 36 as a result of the excessive etching of silicon oxide. This structure is identical with the structure of the example described with reference to FIGS. 1A-1C, and because of this, the structure has the same problem of the declining surface 37 being formed near the groove 34.